1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to a method for etching a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Recently, advancements in the use of magnetoresistive materials have progressed the development of magnetic random access memory (MRAM) devices to function as viable non-volatile memory circuits. In general, MRAM circuits exploit the electromagnetic properties of magnetoresistive materials to set and maintain information stored within individual magnetic memory cell junctions of the circuit. In particular, MRAM circuits utilize magnetization direction to store information within a memory cell junction, and differential resistance measurements to read information from the memory cell junction. More specifically, information is stored within an MRAM cell junction as a bit, the state of which is indicated by the direction of magnetization within one magnetic layer of the memory cell relative to another magnetic layer of the memory cell. In addition, a differential resistance can be determined from differences in the magnetization directions between magnetic layers of the memory cell such that the state of the bit stored in the MRAM cell junction may be read.
Such adaptations of the MRAM cell junction may include one or more magnetic layers having a fixed magnetic direction and one or more other magnetic layers which do not have a fixed magnetic direction. In particular, the magnetic layers within the magnetic cell junction which do not have a fixed magnetic direction may be adapted to change their magnetic direction relative to the magnetic layers having a fixed magnetic direction such that logic states of a bit may be stored. Consequently, the portion of the magnetic cell junction having the layers with a fixed magnetic direction may be referred to as the “reference portion,” while the portion of the magnetic cell junction having the one or more magnetic layers adaptable to change may be referred to as the “storage portion.”
Typically, a magnetic cell junction is formed from patterning a stack of layers such that a structure of a given length and width may be obtained. In some cases, such a patterning process may include wet etching the stack of layers. Such a technique, however, may cause some portions of the stack of layers to be undercut. Consequently, the dimensions of magnetic cell junctions formed from wet etch techniques may vary within an array. In general, variations of cell junction sizes and shapes may cause the amount of current needed to switch the magnetic direction of memory cells to vary, reducing the reliability of the memory array. In particular, size and shape variations of the cell junctions within an array may allow a false bit to be unintentionally written to one or more cells. As such, in an effort to alleviate the undercut problem, dry etch techniques, such as ion milling and reactive ion etching are sometimes employed to pattern magnetic cell junctions. Such dry etch techniques, however, often cause material removed from the stack of layers to be redeposited upon sidewalls of the patterned magnetic cell junctions. In some cases, such a redeposition of material may alter the functionality of the memory array or render the memory array inoperable. In particular, the redeposition of material along the sidewalls of a magnetic cell junction may produce shorts across the tunneling barrier layer of the cell junction, prohibiting the logic state of the magnetic cell junction from being determined.
Consequently, in some embodiments, another technique is employed to define the lateral boundaries of magnetic cell junctions within a memory array. More specifically, in some cases, exposed portions of a stack of layers having a masking layer formed thereupon may be oxidized such that unoxidized portions of the stack of layers underlying the masking layer may define the lateral boundaries of the magnetic cell junction or more particularly, the lateral boundaries of the storage portion of the magnetic cell junction. Such a technique often requires a relatively robust oxidation process, such as a high density plasma oxidation process, in order to oxidize the thickness of the layers within the storage portion of the stack of layers. Controlling the depth of oxidation using a robust oxidation process, however, is often difficult. Consequently, lower layers of the stack of layers may be undesirably oxidized. In particular, layers arranged within the reference portion of the magnetic cell junction may be oxidized. The oxidation of the layers within the reference portion of the magnetic cell junction may cause magnetic poles to form along the ends of the layers, altering the magnetic balance of the reference portion of the magnetic cell junction. In some cases, such a change in the magnetic balance of the reference portion may cause the magnetic cell junction to malfunction, reducing the reliability of the memory array.
Therefore, it would be desirable to develop a method for patterning a magnetic cell junction which does not alter the magnetic balance of the reference portion of the magnetic cell junction. In addition, it would be advantageous to develop a method which does not cause layers within magnetic cell junction to be undercut. Moreover, it would be beneficial to fabricate a magnetic cell junction using a patterning process that is not susceptible to shorts occurring across the junction's metal features.